1. Technical Field
The present invention relates generally to a method of fabricating a semiconductor device, and more particularly, to a method of forming a via contact structure using a dual damascene technique.
2. Discussion of Related Art
As semiconductor devices become more highly integrated, a technique employing multi-layered metal interconnection lines has been widely used. Generally, multi-layered metal interconnection lines are formed of a metal layer having a low resistivity and a high reliability to improve the performance of the semiconductor devices. A copper layer is attractive as a metal layer. However, a copper layer is difficult to pattern using a conventional photolithography/etching technique. Thus, a damascene process has been proposed to obtain fine copper patterns.
A dual damascene process is widely used in formation of upper metal lines that are electrically connected to lower metal lines. In addition, the upper metal lines fill a via hole and a trench region formed in an inter-metal dielectric layer. The via hole is formed to expose a predetermined region of the lower metal line, and the trench region is formed to have a line-shaped groove that crosses over the via hole. Thus, the via hole and the trench region are formed using two separated etching steps.
The dual damascene process is taught in U.S. Pat. No. 6,268,283 to Huang, entitled “Method for forming dual damascene structure”.
FIGS. 1 through 4 are cross-sectional views illustrating a conventional dual damascene process as disclosed in the U.S. Pat. No. 6,268,283.
Referring to FIG. 1, a first insulating layer 204 is formed on a semiconductor substrate having a lower interconnection line 202. An etch stop layer 206, a second insulating layer 208 and a hard mask layer 210 are sequentially formed on the first insulating layer 204. The hard mask layer 210 is formed of a silicon oxide layer (SiO), a silicon nitride layer (SiN) or a silicon oxynitride layer (SiON). The hard mask layer 210 is formed using a chemical vapor deposition (CVD) technique. A first photoresist pattern 212 is formed on the hard mask layer 210. The first photoresist pattern 212 has an opening that defines a via hole. The second insulating layer 208 is not damaged by a developer during formation of the first photoresist pattern 212 because of the presence of the hard mask layer 210. Thus, the hard mask layer 210 can prevent the second insulating layer 208 from being deformed during formation of the first photoresist pattern 212.
Referring now to FIG. 2, the hard mask layer 210, the second insulating layer 208, the etch stop layer 206 and the first insulating layer 204 are sequentially etched using the first photoresist pattern 212 as an etching mask, thereby forming a via hole 214 that exposes the lower interconnection line 202.
Referring to FIG. 3, the first photoresist pattern 212 is removed. A capping layer 216 is then formed on the hard mask layer 210. The capping layer 216 is formed using a plasma CVD process. In general, the plasma CVD process exhibits poor step coverage. Therefore, the capping layer 216 covers only an upper region 218 of the via hole 214. Thus, a void is formed in a lower region 220 of the via hole 214. A second photoresist pattern 224 is formed on the capping layer 216. The second photoresist pattern 224 has an opening that crosses over the via hole 214. A sidewall 222 of the via hole 214 is not damaged by a developer during formation of the second photoresist pattern 224 because of the presence of the capping layer 216.
Referring to FIG. 4, using the second photoresist pattern 224 as an etching mask, the capping layer 216, the hard mask layer 210 and the second insulating layer 208 are sequentially etched to form a trench 226 in the second insulating layer 208. The lower interconnection line 202 exposed by the via hole 214 may be over-etched during formation of the trench 226 because of the void formed in the via hole 214. Thus, the surface of the lower interconnection line 202 may be damaged by the etching process for forming the trench and cause contact failure between the lower interconnection line 202 and an upper interconnection line to be formed in a subsequent process.
Therefore, there is a need for a method of fabricating a via contact structure in a semiconductor device that prevents contact failure between interconnection lines within the semiconductor device.